Controlled collapse chip connection (C4) or flip-chip technology is used for interconnecting high input/output semiconductor devices to substrates via an array of solder bumps. The solder bumps typically comprise a Pb/Sn alloy and are connected to the semiconductor device and substrate at solder joinable contact pads. In many instances, the semiconductor devices are connected to substrates made of materials with coefficients of thermal expansion that differ from the coefficient of thermal expansion of the material of the semiconductor device. Normally the semiconductor device is formed of monocrystalline silicon with a coefficient of thermal expansion of 2.5-3.5.times.10.sup.-6 per .degree.C. The organic substrate is usually formed of polymer impregnated fiberglass having a coefficient of thermal expansion of 30-40.times.10.sup.-6 per .degree.C. In operation, the active and passive elements of the semiconductor device generate heat resulting in temperature fluctuations in both the semiconductor device and the supporting substrate since the heat is conducted through the solder bonds. The semiconductor device and substrate thus expand and contract in different amounts with temperature fluctuations due to the different coefficients of thermal expansion. This imposes both shear and bending stresses along the solder terminals/pads.
The stress on the solder bonds during operation is directly proportional to (1) the magnitude of the temperature fluctuations, (2) the difference in the coefficients in expansion of the material of the semiconductor device and the substrate and (3) the distance of an individual bond from the neutral or central point of the device. In addition, solder bond stresses are inversely proportional to the height of the solder bond, that is the spacing between the semiconductor device and the substrate. The problems associated with stresses at the solder/bond pad interfaces are further compounded by the fact that as solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases. Due to the flexible nature of organic substrates, including those that are fiber reinforced, the substrates tend to warp or bend during processing and temperature fluctuations. This greatly magnifies the problems associated with the destructive stress forces that are placed upon a solder joint between a substrate and a semiconductor device.
FIG. 1A illustrates a typical prior art solder interconnecting structure 10 between a semiconductor device 12 and substrate 14. Device 12 and substrate 14 are electrically coupled by C4 type solder connections 16 that are joined to solder wettable pads 18 on the semiconductor device and to corresponding solder wettable pads 20 on the substrate. The interconnection structure 10 generally comprises a single-layer, epoxy base material commonly known as a "filler".
As mentioned earlier, in prior art solder interconnection structures there are many problems associated with the formation of shear and bending stresses at the solder/bond pad interfaces. These stresses are generally attributable to the difference in the coefficients of thermal expansion of the semiconductor and substrate materials. FIG. 1B illustrates a typical stress distribution 26 generated by shear forces (F) acting upon the apparatus of FIG. 1A due to the thermal expansion of substrate 14 relative to semiconductor device 12. FIG. 1C illustrates a typical bending stress distribution 28 generated by moment forces (M) acting on the apparatus of FIG. 1A due to the thermal expansion of substrate 14 relative to semiconductor device 12. As shown, the maximum shear and bending stresses acting upon the structure are concentrated at or near the facing surfaces 22 and 24 of semiconductor device 12 and substrate 14. More importantly, it is important to note that the stresses tend to concentrate along the interfaces between solder connection 16 and bond pads 18 and 20. This is especially problematic since the adhesion forces within the interconnect structure 10 are typically at a minimum along the solder connection and bond pad interfaces. The thermo-mechanical stress conditions found at the solder and bond pad interfaces will often cause cracks to form along the interfaces which eventually promulgate into the solder connections 16. As a result, the quality and reliability of the electrical connection between device 12 and substrate 14 is greatly reduced. This can often cause a device to fail resulting in lower manufacturing yields which can be very costly. Moreover, such thermo-mechanical stresses reduce the life and stability of the solder bond joints.
What is needed then is a solder interconnection structure which solves the aforementioned problems associated with concentrated stresses at the solder bond joints of semiconductor devices and their supporting substrates. As will be seen, the present invention provides a solder interconnection structure that reduces the stress concentrations at the solder connection and bond pad interfaces and, thus enhances the reliability of the electrical connection between a semiconductor device and supporting substrate.